This application relates to programmable logic array integrated circuits (“programmable logic devices”), and more particularly, to input-output circuitry for programmable logic devices.
Programmable logic devices are integrated circuits that may be programmed by a user to perform various logic functions. Some currently-available programmable logic devices have I/O driver circuitry that can be selectively configured to accommodate different I/O signaling standards. This flexibility enhances the usefulness of such devices, because they may be used in various system environments and may communicate with a broader range of other devices than would otherwise be possible. However, substantial performance penalties may arise if the input-output circuitry of a programmable logic device is made too flexible.
On some currently-available programmable logic devices the transmitters (output drivers) in the I/O circuitry may be made more programmable than the receivers (input drivers) to take advantage of the less sensitive nature of the transmitters to performance penalties when adding support for multiple signaling standards. On these devices higher speed I/O circuits may be provided with less programmability to maximize their performance. Performance is enhanced further by reducing the amount of signal conductor area that immediately underlies the flip-chip solder bump pads at the ends of the I/O ines on the programmable logic device.
It is therefore an object of the present invention to provide programmable logic devices that have input-output circuitry with both flexibility and high performance.